The load current of a modern central processing unit (CPU) is highly dynamic and changes very quickly from low to high and from high to low. A CPU current transient may occur within 1 microsecond, for example, which is less than the typical switching period of conventional voltage regulators. It is desired to provide a DC-to-DC voltage regulator with a control loop (e.g., voltage mode or current mode control loop) that can provide a nearly real time transient response to the load change to regulate the correct output voltage.
In a conventional constant frequency pulse width modulation (PWM) scheme, a single ramp signal or dual ramp signals are often induced by a constant frequency synchronous clock to be generated as a reference signal and then compared with an output voltage error signal to generate a pulse width modulation signal for regulating the output voltage. Herein, the output voltage error signal is varied along the change of a difference between an output voltage and a target voltage. As illustrated in FIG. 1, a timing diagram associated with a scheme in the prior art is shown. The scheme is that a single ramp signal RAMP is induced by a constant frequency synchronous clock CLK to be generated as a reference signal and then compared with an output voltage error signal COMP to generate a pulse width modulation signal PWM. In particular, a single pulse of the synchronous clock CLK functions as a trigger signal for triggering the switching between ramp up and ramp down of the single ramp signal RAMP. Adjacent two time points of the ramp signal RAMP crossing with the output voltage error signal COMP respectively are used to determine a start point (i.e., generally a switching trigger point of the pulse width modulation signal PWM) and an end point of an ON-time of the pulse width modulation signal PWM.
However, it can be found from FIG. 1 that, since the ramp signal RAMP is constrained by the synchronous clock CLK to be fixed, in the conventional constant frequency PWM scheme, the ON-time of the pulse width modulation signal PWM is difficult to provide a real time response to the transient (e.g., the surge of the COMP in FIG. 1) of the output voltage error signal COMP caused by the load change/transient.
In another aspect, a constant ON-time pulse width modulation scheme (i.e., generally related to COT system) has been disclosed by such as U.S. Pat. No. 7,714,547 (the disclosure of which is fully incorporated by reference herein), and is often used for low duty cycle “Buck” converters because it provide fast transient response and does not require compensation for control loop stabilization. In the constant ON-time control scheme, when the regulated output voltage falls below a reference threshold, a constant ON-time DC-to-DC converter/regulator delivers energy to its output load whereby the amount of energy delivered by the converter is determined by the ON-time pulse of the converter. However, since the ON-time is constant, the constant ON-time control scheme could not self-correlate a suitable ON-time to meet the energy requirements of different load conditions after any load transient, encountering the load transient regulation issue.